https://en.wikichip.org/wiki/phytium/microarchitectures/mars_ii

Mars II is the successor to Mars I, an ARM server SoC microarchitecture designed by Phytium Technology for the Chinese server market.

Process technology[edit]

Mars II is largely a shrink of Mars I, from 28 nm process to a 16 nm FinFET process.

Architecture[edit]

Key changes from Mars I[edit]

• 16 nm process (from 28 nm)
• 15% higher frequency (2.3 GHz, up from 2 GHz)
  • higher FLOPS performance (588.8 GFLOPS, up from 512 GFLOPS)
• -25% lower power (96 W TDP, down from 120 W)
• Core
  • FTC-662 (from FTC-661/0)
• System memory
  • Panel directly connected to 1 MCU (Previously linked to CMC)
    • DDR4 (from DDR3)
    • Higher data rates (2400 MT/s, up from 1600 MT/s)

This list is incomplete; you can help by expanding it.

Block diagram[edit]

Entire SoC[edit]

Panel[edit]

Core[edit]

Main article: Xiaomi Core

See Xiaomi Core.

Overview[edit]

Mars II is Phytium's second-generation many-core server processor based on a custom ARM core. The Mars II is largely a shrink of their first-generation SoC but it does introduce a number of enhancements. Fabricated on a leading-edge 16 nm FinFET process, the new SoC is considerably smaller than the prior die, offers higher frequency, and lower power. Mars II features 64 custom ARMv8.0 cores operating at up to 2.3 GHz for a total of 588.8 GFLOPS. The SoC incorporates high DDR4-2400 memory channels and includes 33 PCIe Gen 3.0 lanes.

Package[edit]

Package	FCBGA-3576
Dimensions	61mm x 61mm
Bumps	11916
Contacts	3576

Die[edit]

Panel[edit]

SoC[edit]

• 16 nm process (16FF+) GL
• 1 Poly, 11 Metal layers, RDL
• 6,000,000,000 transistors
• 370 mm² die size
• 2.3 GHz @ 0.9 V, 96 W

All Mars II Processors[edit]

Bibliography[edit]

• HPC Asia 2019